MSP430, CCS, 8MHz Clock

MSP430, CCS, 8MHz Clock

※ msp430.h 를 사용하는 소스입니다.

Did you have a look at the example codes for the MCU that is provided by TI for almost every processor?

www.ti.com/lit/zip/slac536

The following examples show how to set up the clocks:

msp430fr59xx_cs_01.c       Configure MCLK for 8MHz operation
msp430fr59xx_cs_02.c       Configure MCLK for 16MHz operation
msp430fr59xx_cs_03.c       Output 32768Hz crystal on XT1 and observe failsafe
msp430fr59xx_cs_04.c       ACLK = XT1 = 32768Hz, SMCLK= XT2 = 8MHz, MCLK = DCO
msp430fr59xx_cs_05.c       Using LFXT in bypass mode, failsafe operation shown

0. 참고 사항

• [MSP430Ware] / msp430fr59xx_cs_01.c
• [MSP430Ware] / www.ti.com/lit/zip/slac536
  
• http://e2e.ti.com/support/microcontrollers/msp430/f/166/p/368560/1297094
• https://github.com/achopra6/MSP430FR6989/blob/master/timer.c
• [MSP430FR6989 DataSheet] / http://www.ti.com/lit/ds/symlink/msp430fr6989.pdf
• [MSP430FR6xx User's Guide] / http://www.ti.com/lit/ug/slau367o/slau367o.pdf

1. 소스 설명

full 소스는 아래 github를 통해 확인하세요.

// Clock System Setup     CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers     CSCTL1 = DCOFSEL_6;                       // Set DCO to 8MHz     CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;  // Set SMCLK = MCLK = DCO     // ACLK = VLOCLK     CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;     // Set all dividers to 1     CSCTL0_H = 0;                             // Lock CS registers

2. 소스

• https://github.com/sglee0223/msp430/tree/master/8MHz_Clock
  

3. 결과